By Bramhananda Marathe,Sandhya Nerale
The goal of this e-book is to supply perception and instinct into the analog and analog-mixed sign procedure verification. it's also a trip the writer of this e-book has been via which will take on functional layout and verification demanding situations with nation of artwork analog and combined sign designs.
Motivation for authoring this book
The electronic layout verification ability set is particularly various than analog layout and verification. generally, the analog block point verification is played by way of the analog designers, and electronic layout verification is played via electronic layout verification engineer. loss of go area ability set makes it tough to accomplish verification at mixed-signal point. as a result, both analog clothier engineer may still research complex electronic verification ideas or electronic layout verification engineer include analog verification to develop into analog-mixed sign verification engineer. This ebook is written protecting this new development in brain, for that reason it covers electronic layout basics, electronic layout verification in addition to analog layout basics, and analog functionality verification.
Organization of this book
Keeping the readers of analog verification or electronic layout verification historical past in brain, the publication has first five chapters excited about the basics of the analog layout, electronic layout, and its verification. bankruptcy 6 and bankruptcy 7 makes a speciality of the analog-mixed sign layout verification and behavioral modeling respectively. bankruptcy eight is devoted to the low energy verification ideas.
Chapter 1: creation to Analog combined sign Verification
This bankruptcy discusses concerning the evolution of the verification methodologies, heritage of analog-mixed sign designs, functions, and destiny developments.
Chapter 2: Analog layout basics
The function of this bankruptcy is to offer an outline of the analog layout basics for electronic layout history engineers. significant concentration is given on analog habit, layout standards and their inspiration instead of layout themselves, corresponding to voltage/current reference, a number of the easy key analog layout houses similar to achieve, band width, fundamentals of jitter, eye diagram, and so forth.
Chapter three: electronic layout basics
In this bankruptcy, we clarify electronic layout move, combinational and sequential good judgment layout basics, layout for testability, innovations of timing, and timing verification.
Chapter four: Analog Verification
This bankruptcy specializes in analog functionality verification and practical verification lower than the context of combined sign layout hierarchical verification instead of the aspect functionality research of the designs themselves.
Chapter five: electronic layout Verification
This bankruptcy explains the instruments and methodologies which are advanced over the interval which are predicated on predictable caliber and verification potency. The bankruptcy comprises the sections at the assurance pushed verification (CDV) technique, statement dependent verification (ABV) method, and assessment of the CDV utilizing Open Verification technique (OVM).
Chapter 6: Analog-Mixed sign Verification
This bankruptcy discusses concerning the AMS verification levels, selecting the right abstraction of DUT for a given verification problem, AMS verification making plans, testplanning for AMS layout verification, and testbench improvement with re-use in brain.
Chapter 7: Analog Behavioral Modeling
This bankruptcy explains in regards to the functions of analog behavioral types, modeling technique, basic examples of varied analog behavioral modeling types, collection of accuracy point of the versions in accordance with the verification plan, version verification, and signoff.
Chapter eight: Low strength Verification
The goal of this bankruptcy is to provide an explanation for the low strength layout verification demanding situations, key low energy layout parts, low strength layout suggestions, low strength layout and verification cycle, testplanning for low strength layout verification, strength acutely aware electronic, and AMS simulations
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Additional info for Analog-Mixed Signal Verification
Analog-Mixed Signal Verification by Bramhananda Marathe,Sandhya Nerale